1. Field of the Invention
The present invention relates to the field of electrically programmable read-only memories. More particularly, the present invention relates to fabricating high voltage, high reliability transistors in memories employing floating gate memory devices.
2. Art Background
Metal-oxide-semiconductor ("MOS") electrically programmable read-only memories ("EPROMs") frequently use memory cells having electrically isolated gates, typically termed "floating gates ". The floating gates are typically surrounded by a dielectric insulator and formed from a polycrystalline silicon (polysilicon) layer. The electrical insulation is typically provided by a silicon dioxide layer. Information to be stored in the memory cell is stored as electrical charge on the floating gates. Charge is transferred through the silicon dioxide layer to the floating gates by a variety of mechanisms such as avalanche injection, channel injection, tunnelling, etc., depending on the construction of the memory cells. The charge stored on the floating gate affects the surface channel conductivity in the memory cell. If the surface channel conductivity is above a certain level, the memory cell is deemed to be programmed in one binary state. Alternatively, the conductivity is below a different level, the memory cell is deemed to be programmed in the other state.
The memory cells take a variety of forms in the prior art and are in some cases erased by exposing the memory array to ultraviolet radiation. In other cases, the memory cells are electrically erasable, and are termed EEPROMs. An example of a EEPROM memory cell is disclosed in U.S. Pat. No. 4,203,158. The invention disclosed in the present application is used with an electrically erased memory EEPROM cell referred to as a "flash" EEPROM. The flash EEPROM cell used in connection with the present invention is described in co-pending applications Ser. No. 253,775, entitled "Low Voltage EEPROM Cell", filed Oct. 5, 1988 now abandoned, and in Ser. No. 407,645, entitled "Apparatus for Providing Block Erasing in a Flash EPROM", filed Sep. 15, 1989, now U.S. Pat. No. 5,065,364, both assigned to the assignee of the present invention.
Referring briefly to FIG. 1A, a cross-sectional view of a typical prior art floating gate flash EEPROM cell 5 is shown. In FIG. 1A, the flash memory cell 5 is formed on a silicon substrate such as the p-type substrate 15. The flash cell includes a pair of spaced-apart doped regions 12 and 13 disposed in substrate 15. Specifically, region 13 comprises a source, and region 12 comprises a drain, source 13 and drain 12 defining an active silicon region 4 and a channel therebetween. A polysilicon floating gate 10 is disposed above and between drain 12 and source 13 and insulated therefrom by a thin layer of silicon dioxide or other electrically insulative layer 14. Insulative layer 14 is generally known as the gate or tunnel oxide, having a typical thickness of approximately 110 angstroms (.ANG.). The floating gate 10 is insulated from a second control gate 11 disposed above floating gate 10 and insulated therefrom by an interpoly dielectric layer 9. Interpoly dielectric layer 9 may be variously formed of a single layer of silicon dioxide, or of an oxide/silicon nitride/oxide multilayer dielectric of appropriate thickness. The control gate 11 is fabricated from a second layer of polysilicon deposited subsequent to the interpoly dielectric layer 9. In some cases control gate 11 consists of a two-layer stacked structure, having polysilicon deposited on the interpoly dielectric followed by tungsten silicide, the two-layer structure acting to reduce the resistivity of control gate 11. At the completion of processing, floating gate 10 is completely surrounded by dielectric insulative layers, and therefore electrically "floats".
Programming, reading, and erasing of flash memory cells is well documented in the art and are, for example, described at length in the Memory Components Handbook published by Intel. Flash cells are programmed by setting the source 13 to ground or zero volts, connecting the drain to a 7 volt power supply, and raising the control gate 11 to programming voltage equal to 12 volts. Under these nominal conditions, hot electron injection occurs from the channel region between source 13 and drain 12 through the tunnel oxide layer 14. To read a programmed cell, ordinary MOS supply voltages are used wherein the gate potential is raised to 5 volts, and the drain is set slightly positive relative to the source. In contrast to programming the flash cell 5, when erasing a flash cell, the drain 12 is permitted to float, the control gate 11 is grounded, and a potential of approximately +12 volts is connected to the source 13. When thus connected, electric charge is removed from the floating gate 10 through tunnel oxide 14.
Although the flash memory cells themselves may be counted on to reliably be programmed and erased many thousand of times, such reliability is guaranteed in highly scaled flash cell and peripheral transistors because the high programming voltages are only briefly connected to a flash cell and the scaled peripheral transistors. A representative scaled peripheral transistor 6 constructed according to typical prior art methods is shown in FIG. 1B. In FIG. 1B, the peripheral transistor 6 is seen to have a slightly thicker (175 .ANG.) peripheral gate oxide 16 formed of thermal silicon dioxide over active silicon region 7. Thicker peripheral gate oxide 16 does not permit tunneling as in the case of flash cell tunnel oxide 14 (FIG. 1A). Moreover, scaled peripheral transistor 6 has oxide spacers 18, which modify source region 18a and drain region 18b diffusion profiles to include, respectively, tip regions 17a and 17b. The "two-tiered" source-drain structure is frequently used to minimize hot carrier effects in highly scaled devices. The scaled peripheral transistor 6 is turned on or off by connecting appropriate; voltages to peripheral control gate 19. The peripheral control gate 19 is formed of the second polysilicon layer only, dispensing with the first polysilicon layer 10 (FIG. 1A) and the interpoly dielectric layer 9 (FIG. 1A).
If a 12 volt potential were continuously applied to a transistor having only the thin (110 .ANG.) tunnel oxide layer 14 (FIG. 1A) or scaled peripheral gate oxide 16 (FIG. 1B) to withstand the high voltage, degradation of either oxide may be expected to occur after some time due to the extremely high electric field (of order 10.sup.7 v/cm) impressed across the thin oxide. The foregoing is especially true in cases of the programming voltage source switches which switchably connect the flash cell transistors to the programming voltage high voltage power supplies. Unlike the flash transistors 5 in the array or peripheral transistors 6 in the program or erase circuitry which only briefly see programming or erase voltages when the cell is either programmed or erased, the source switches are constantly, for their lifetimes, exposed to the high programming voltages. Due to constraints in MOS device fabrication, all transistors must be formed at the same time on the chip, regardless of the application of a particular device during operation of the circuit. Heretofore, producing different transistors for different applications including high voltage applications within one circuit has not been problematic to the extent that transistor dimensions have generally been consistent with voltage potentials applied across those transistors.
However, in the quest for ever-smaller devices to increase circuit speed and packing densities, devices are being scaled more and more. Scaling is a collective term referring to procedures wherein circuit dimensions and device structures are shrunk in proportion to one another to produce a smaller device which still functions according to parameters known to be functional on larger unscaled devices. One natural consequence of device scaling is that when all transistor dimensions are reduced, the insulative gate oxide between the substrate channel and the control gate is reduced proportionally. Although reducing the thickness of the gate oxide of the peripheral transistors may be desirable to enhance the performance or size of the flash memory itself, the thinner oxide produced for the scaled array and peripheral devices will be inherently problematic for those peripheral devices exposed to voltages higher than are applied to any of the array cells and for longer periods of time. Again, a leading example of devices which suffer as a result of scaling are the transistors functioning as source switches connecting flash memory cells to the programming voltage power supplies. Whereas the flash memory cell and the majority of peripheral transistors may only be connected to the programming voltage for a few milliseconds to program or erase the cell, the source switch is continuously exposed to the high voltage power supply used for programming and erasing the flash memory cell. Using the scaled peripheral transistor oxide thickness for the source switch gate oxide, source switch reliability cannot be guaranteed in the absence of additional and costly processing to separately fabricate special high voltage transistors to function as the source switches.
A designer designing transistors in a flash application is thus faced with a paradox where some of the transistors must continuously withstand the 12 volt (or higher) potential, but in order to scale peripheral transistors in order to obtain optimal speed and packing density, the gate oxide of the source switch transistors is reduced to the thickness of the peripheral transistor gate oxide, or approximately 175 .ANG. angstroms. Because 175 .ANG. oxides will not reliably sustain 12 volt programming voltages, prior art solutions require extra processing steps to produce peripheral transistors with thicker gate oxide. The paradox is further exacerbated in that only very few high voltage source switches are required in a flash memory in comparison to the large number of array cells and high performance scaled peripheral transistors. Under ordinary cost-benefit analysis, improving switching device reliability could not justify the added complexity, cost and cycle time of the additional special processing required to fabricate extremely few, albeit important, devices.
The present invention discloses a method for producing high voltage transistors contemporaneously with the scaled flash array transistors and scaled peripheral transistors without adding any processing steps or making existing steps more complex. As will be explained in more detail in the following paragraphs, the present invention improves upon the prior art by enabling fabrication of robust non-scaled transistors with thicker gate oxide on the periphery of the flash memory circuit without requiring additional dielectric deposition or definition processing steps. The present invention takes full advantage of the existing prior art processing steps, including masking layers and first and second polysilicon layer thicknesses to produce a thicker gate oxide in the peripheral transistors operating as source switches for the high voltage programming voltages.